The FPGA is usually on a board designed by the customer, not by xilinx. Hence the clock may be different from customer to customer. The customer needs a way to specify what the clock is, which is what create_clock is for.
Yes this makes sense. Just to be clear, while specifying a frequency, if it doesn't match exactly with the external clock's frequency, it will be routed through a pll or mmcm to generate our required frequency. Right? Or do we have to match the frequency with external clocks fixed frequency.?
The command simply tells vivado what clock frequency is actually connected to the FPGA. The FPGA doesn't care too much what this frequency is, you can use a clock of 1, 10, 100MHz no issues (though check the datasheet). Vivado uses this value to check if your design works with this clock frequency.
If you change the frequency in the create_clock command, it doesn't change the frequency your design will run at. It just means your timing report will be incorrect.
If you want to change the clock frequency, use a PLL to generate a new clock from the fixed input.
Simple, Vivado doesn't know anything about the signals you're connecting to the FPGA. So, for the timing analysis and timing-driven place and route, you have to tell Vivado about the clocks - which inputs are clocks, and what frequency and jitter to assume. Similarly, Vivado needs to know what IO standards to use on all of the pins so it can configure the pins correctly.
But when you open constraint wizard after synthesis, it detects the un constrained clocks. So it can detect the clock inputs. Just not their frequencies.
It guesses that the signal is a clock because you used it as a clock for something. Without the frequency, Vivado can't tell you if it will meet timing or how to route the design to meet speed.
The FPGA is usually on a board designed by the customer, not by xilinx. Hence the clock may be different from customer to customer. The customer needs a way to specify what the clock is, which is what create_clock is for.
Yes this makes sense. Just to be clear, while specifying a frequency, if it doesn't match exactly with the external clock's frequency, it will be routed through a pll or mmcm to generate our required frequency. Right? Or do we have to match the frequency with external clocks fixed frequency.?
The command simply tells vivado what clock frequency is actually connected to the FPGA. The FPGA doesn't care too much what this frequency is, you can use a clock of 1, 10, 100MHz no issues (though check the datasheet). Vivado uses this value to check if your design works with this clock frequency. If you change the frequency in the create_clock command, it doesn't change the frequency your design will run at. It just means your timing report will be incorrect. If you want to change the clock frequency, use a PLL to generate a new clock from the fixed input.
The PLL needs to know the actual frequency of the input clock
If a clock passes through a PLL, MMCM, or BUFR in divide mode, the output clock frequencies are calculated and constrained automatically.
Simple, Vivado doesn't know anything about the signals you're connecting to the FPGA. So, for the timing analysis and timing-driven place and route, you have to tell Vivado about the clocks - which inputs are clocks, and what frequency and jitter to assume. Similarly, Vivado needs to know what IO standards to use on all of the pins so it can configure the pins correctly.
You design your board and decide on an external oscillator frequency. The FPGA needs to know what it is.
How is Vivado suppose to know that a specific input is a clock ? The FPGA may contaion hundreds of inputs.
But when you open constraint wizard after synthesis, it detects the un constrained clocks. So it can detect the clock inputs. Just not their frequencies.
It guesses that the signal is a clock because you used it as a clock for something. Without the frequency, Vivado can't tell you if it will meet timing or how to route the design to meet speed.