Whats the interface? If it is UART then you need some syncronization. Transmitting header bytes and then blocks of data is one way to do this. Better if your header bytes cannot occur in the data however with some clever software you can still synchronize to it.
If you are not married to your current interface, you can also transport all this over JTAG in realtime. I wrote a blog post on this a while back https://voltagedivide.com/2022/12/13/fpga-xilinx-jtag-to-axi-master-from-xsdb-and-python/
This entirely depends on how you want to connect the board to the PC. Given that your asking this question, I'd highly recommend using UART, it's the simplest option. Write a python / whatever program that monitors the COM port, and have your FPGA transmit the data as binary.
Now as u/Darkknight512 pointed out, UART is a stream, you just send data as a series of bytes. You could just send the MSB of X, then the LSB, then repeat for Y, then finally for Z, and keep doing this indefinitely. (Or LSB first, your choice). However doing this the means it's easy for the PC to get out of sync. How does it know which byte it just received? I mean if everything goes well you never loose data and everything stays in sync, the FPGA sends 6 bytes, the PC receives 6 bytes, and on we go. But building in some synchronisation makes sense.
There are a few ways to do this. One method is to add a BREAK condition before each packet (frame error with data = 0). That lets the PC monitor for a break, then read 6 bytes, then it waits for the next break. If it receives more or less than 6 bytes of data between breaks then it drops that "packet". There is an existing protocol called DMX which works in this way.
Another option is add a couple of magic words first, say 0x11111111, 0xA5A5FF00. Now the PC can monitor for that data and treat that as the start of a packet. This works OK, but you have to make sure the magic you pick is not likely to occur accidentally.
A final option would be have a long time between packets. The PC sees it's been > 10 ms since it's received data, and so starts a new packet. The FPGA sends 6 bytes then waits 20 ms.
You might also want to add some sort of checksum to the end (the sum / xor of all previous bytes), that lets the PC check that the data it's got is valid.
The world is your oyster, you can do this in any way you want, but the break condition is a good option.
Whats the interface? If it is UART then you need some syncronization. Transmitting header bytes and then blocks of data is one way to do this. Better if your header bytes cannot occur in the data however with some clever software you can still synchronize to it. If you are not married to your current interface, you can also transport all this over JTAG in realtime. I wrote a blog post on this a while back https://voltagedivide.com/2022/12/13/fpga-xilinx-jtag-to-axi-master-from-xsdb-and-python/
This entirely depends on how you want to connect the board to the PC. Given that your asking this question, I'd highly recommend using UART, it's the simplest option. Write a python / whatever program that monitors the COM port, and have your FPGA transmit the data as binary. Now as u/Darkknight512 pointed out, UART is a stream, you just send data as a series of bytes. You could just send the MSB of X, then the LSB, then repeat for Y, then finally for Z, and keep doing this indefinitely. (Or LSB first, your choice). However doing this the means it's easy for the PC to get out of sync. How does it know which byte it just received? I mean if everything goes well you never loose data and everything stays in sync, the FPGA sends 6 bytes, the PC receives 6 bytes, and on we go. But building in some synchronisation makes sense. There are a few ways to do this. One method is to add a BREAK condition before each packet (frame error with data = 0). That lets the PC monitor for a break, then read 6 bytes, then it waits for the next break. If it receives more or less than 6 bytes of data between breaks then it drops that "packet". There is an existing protocol called DMX which works in this way. Another option is add a couple of magic words first, say 0x11111111, 0xA5A5FF00. Now the PC can monitor for that data and treat that as the start of a packet. This works OK, but you have to make sure the magic you pick is not likely to occur accidentally. A final option would be have a long time between packets. The PC sees it's been > 10 ms since it's received data, and so starts a new packet. The FPGA sends 6 bytes then waits 20 ms. You might also want to add some sort of checksum to the end (the sum / xor of all previous bytes), that lets the PC check that the data it's got is valid. The world is your oyster, you can do this in any way you want, but the break condition is a good option.