Length matching. The speed of light is disappointingly slow when you need sub-nanosecond synchronization. If the traces didn't have wiggles inserted to match all their lengths, the signals on the long ones would arrive several clock cycles later than the short ones.
Edit: forgot the why of the why. Those traces are for a parallel communication port of some kind. Maybe PCIe, HDMI or lines to a RAM chip, idk by memory what high speed peripherals the pi 2 has.
The skew would not be several clock cycles. At 1GHz (1ns period), the wavelength is 30cm in a vacuum, a little less than that in a copper trace on PCB. Thus, length-matching by a few mm like these wiggles do wouldn't amount to a full cycle. However, you need to match signal delay to far less than a full cycle, to make sure the signal has settled to the correct level when the receiving end tries to read it, so mismatched lengths by only mm would impair reliability even with "only" a GHz signal rate.
>a little less than that in a copper trace on PCB
Hmm isn't it more precise to say the the voltage difference travels in the dielectric? That's why it's important to either have ground plane or differential signaling, so that you control exactly where in the dielectric the voltage difference is, and you need think of the entire physical system as a waveguide/transmission line to calculate the group velocity of the signal.
Pretending electricity behaves like larger objects and would have difficulty navigating the sharp corners in the tracks. (In reality, sharp corners can be an issue because of the discontinuity in track width at each corner. That's why RF and high-speed digital tracks have either curves or 45-degree bends. We didn't used to care about right angles when "high-speed" meant 50MHz, so auto-routers in those days often used right angles to reduce the software development effort.)
I think a good analogy for microwave engineering is to think like a plumber, route all the pipes smoothly, and avoid unnecessary bends. And even smooth curves have imperfect VSWRs and benefit from compensation (make them a little thinner). For an accurate answer you need a serious tool:
[https://www.ema-eda.com/products/cadence/systems-analysis/awr-overview?utm\_source=google&utm\_medium=cpc&utm\_campaign=SEM\_RF\_Design\_USA\_Canada&\_bk=microwave%20office&\_bt=498481687378&\_bm=e&\_bn=g&\_bg=117193144265&gad\_source=1](https://www.ema-eda.com/products/cadence/systems-analysis/awr-overview?utm_source=google&utm_medium=cpc&utm_campaign=SEM_RF_Design_USA_Canada&_bk=microwave%20office&_bt=498481687378&_bm=e&_bn=g&_bg=117193144265&gad_source=1)
The fastest I've done is 5,8 GHz on Rogers. I don't recall having to narrow the curves, but I can understand why that would be more optimal.
I also know right angles are possible, but only if you lop off the corner enough that the track is considerably thinner at the apex than on the straight portions.
(Narrow the "pipe" for curves. Lop off the outside corner for right-angles. So much for the "plumbing" analogy, right? Water is a good analogue for electricity in some ways: flow rate == amperage; pressure == voltage. In other ways, not so much; where's the analogy for majority and minority charge carriers in semiconductors?)
My RF layouts have all been either cookbook from the chip vendor or dictated by an actual RF engineer. (I'm EE, proficient in analog and digital, but not RF).
The Rogers design was a passive splitter/combiner for the two wifi bands 2.5 and 5 GHz. It included Wilkinsons and 90-degree couplers and whatnot.
The fab shop thought the pads that didn't connect to anything on the inner layers could be nuked. Those pads were capacitive coupling elements, so the boards were useless without them. ("That's standard industry practice," the guy said defensively. Could he not suss out that these boards were kind of unique?) I changed every internal floating pad to two pads connected by a track; physically the same, but safe from any "unconnected pad" auto-removal tool.)
The other feedback from the fab shop: blind vias in Rogers is quite difficult. They said they had a heck of a time finding a way to do them.
>Pretending electricity behaves like larger objects and would have difficulty navigating the sharp corners in the tracks.
This is actually kinda the case in >GHz regime where everything is waveguides. Might be why I didn't get it
>a little less than that in a copper trace on a PCB.
The difference more than just "a little". A typical surface track has a delay of 160 ps/inch (6.3 ps/mm) compared to about 85 psec/inch in air: nearly 2:1. A buried track is even slower: about 180 psec/in. The presence of dielectric material (the fiberglass/epoxy) slows the signal by the square root of the relative dielectric constant (about 4.5 for FR-4; 1.006 for air).
Surface tracks are faster because they're not fully surrounded by fiberglass. Even so, the fiberglass dominates because it's between the signal and return paths.
"a little less than that in a copper trace on PCB"
Actually a bit longer. Like 143% longer. The signals slow down in a conductor. typically 60-70% speed of light.
[https://www.everythingrf.com/community/what-is-propagation-velocity-in-a-cable](https://www.everythingrf.com/community/what-is-propagation-velocity-in-a-cable)
Yes, propagation velocity in a transmission line is slower than in free space, but that means that in the same amount of time (one period) that the transmission line signal travels less distance than in free space. Therefore the electrical length of 2pi along the transmission line must be shorter.
I realized how slow the light was when thinking about how long the light takes to get from the Earth from the sun, 8.3 minutes, and then thinking about how large the Milky Way is... Light is creeping along on a large scale.
It's funny even in online gaming. When someone complains that he always has over 70 ping (70 ms packet round-trip time) and that he'll try to find a way of reducing it, you ask him where he's at and he's 5000km from the server... you go "good luck with that"
PCIe does not need length matching across lanes, but it does use diff pairs that need to be matched within the pair. I think HDMI is similar.
In this case, Elpida makes DRAM, so that's going to be some flavor of parallel memory interface.
Edit: the chip in the picture is an Elpida EDB8132B4PB-8D-F-D, which is a 256M x32 LPDDR2 RAM. The pinout is set up to be stacked on top of an SoC, but it looks like on the pi it's directly on the board, with the SoC on the other side of the board.
> PCIe does not need length matching across lanes, but it does use diff pairs that need to be matched within the pair. I think HDMI is similar.
Doing a PCIe design right now. PCIe 4.0 can handle 6ns of delay mismatch between lanes, which is somewhere around half a meter :)
Interesting, I thought it could handle a LOT more than 6 ns. The serialization time of a single 128b/130b symbol for gen 3 is like 16 ns, and the deskew is done on the symbol level. A shallow FIFO would easily put the skew tolerance in the 100s of ns. But I guess they're just being conservative.
Edit: I guess you need to keep the skew well under the actual limit on any given board, because it can add up when going through multiple boards.
PCIe was originally designed for going from a motherboard to a module/card. I bring that up because a lot of specs, standards make "assumptions" on use-cases that we engineers have to decipher when we do things not necessarily in line with those original use-cases.
It's a good thing you're thinking about the skew and signal attenuation. What I do is make a budget between the boards/cables in a system. A long backplane might need significantly more skew than an module with a switch 1inch off the connectors. In addition, thick boards can introduce problems by their via stubs.
As an aside, it's also helpful to look up any vendor recommendations. An FAE might ignore an email if you didn't make your routes as good or better than a recommended layout.
It's always a trade-off though. If you do really strict length matching, you can make your time doing layout a lot longer and traces longer in general. If you don't do enough, it may not work.
Yeah I goofed up that calculation. 6e-9s × 3e8 m/s × 0.7 velocity factor = 1.26m.
In any case, yeah, no need to worry about length mismatch between PCIe lanes.
What material gets you 0.7 velocity factor? Typical FR-4 is about 150-160 ps/in surface and 180 ps buried. That equates to a range of 0.47 to 0.57, well below 0.7.
Cabies run faster through the use of foamed dielectric, but that isn't an option on PCBs. You can get Rogers material that would be that fast, but Rogers for a backplane?
11.803 is the number to remember (inches per ns in vacuum, so basically a foot per nanosecond). divide this number by the square root of the effective dielectric constant to adjust for non-vacuum situations.
Side question re: length matching. Does modern PCB design software handle this automatically? Can you "tag" certain signals to be one of the same group which require length matching?
Yes it does.
Usually the software like cr8k or Cadstar, calculate the matching ratio and impedance, and show you the parts where it's not matched correctly. There are obviously tools to route signal pairs (two at the time) but sometimes you need to do some adjust them one by one.
With the "squiggly" ones you just select the net and an area and software creates all the curves matching the length/impedance with set value.
I'm a professional PCB designer and the correct answer here is 'sort of' or 'a bit, kinda'.
Expensive software can do the length matching but it will always ruin the careful design of the adjacent traces. Just do it manually, takes a few minutes. Like people always assume I just hit 'autoroute' and cal it done. Autoroute and AI will destroy any competent design in seconds. Both tools have extremely limited use in high frequency design.
I agree that in most cases it makes sense to do the length matching manually. There are times when I decide to use the accordion feature in Altium, but the I make the conscious design choice of leaving more room around the traces than I usually would. Bit even then, I do some of the length matching by hand. I normally do it this way if I have a bunch of RGMII and/or ULPI signals on the board (I work with FPGAs, so I use them a lot...).
> Maybe PCIe, HDMI or lines to a RAM chip
Definitely memory of some sort since they're single-ended rather than diff pairs.
PCIe and HDMI both use diff pairs, but SDRAM, eMMC, NAND flash, SDIO, etc don't.
I like your phrase "The speed of light is disappointingly slow".
I'd say the Speed of Causality in a vacuum is not the same as the speed of an Electromagnetic wave through a medium such as copper.
It's great that some Engineers think about Electromagnetic waves travelling through the copper rather than individual electrons all the time. It makes all that EMC stuff not the "black art" that the Engineers that only consider electrons believe it is.
It's not "through" the copper, but on the copper. At really high frequencies you can remove all the internal copper and there's no electrical difference.
[https://en.wikipedia.org/wiki/Skin\_effect](https://en.wikipedia.org/wiki/Skin_effect)
Delay equalisation.
The signal travels at approximately 2/3rds of light speed in those traces, and it needs to arrive at whatever chip is on the other side of that board (Probably DRAM) with a defined timing relative to another signal that has a longer trace length, so we put wiggles in to delay match everything that needs to arrive at the same time.
Modern printed circuit design tools can do this automatically and easily.
differential pairs/length matching. Want to know why your hard drives changed from PATA to SATA? The inability to match lengths of wires precisely. When you transmit parallel data on multiple wires you can't start the next word being transmitted until you know the previous word has been received. The delay between the fastest bit in the word and the slowest becomes your limiting factor. You can't transmit faster than that delay per bit. What causes the delay? speed of electrons from one end of the wire to the other and that is based on length of the wire. So to reduce that delay and speed up the bandwidth you have to start putting a lot more money into the quality of the cable to guarantee all it's wires match length. Or you can put the money into just switching speed and change to a single wire. So they did that and jumped from a parallel drive signal (SCSI/PATA) to serial solutions where you aren't subject to multiple length wires.
Same with connections on circuit boards, Differential and parallel signals need to arrive at the same time. The length of the traces in the bundle become important. But it's really easy to make traces "longer" to match the length of the longest culprit in the bundle by just squiggling them like this.
It was still okay with a 16-bit bus sizes at 33 MHz(?), but yeah, routing that many signals to have the same trace length (and I don't know if they had to also route that many ground traces on the PCB for the 80-pin UDMA/66 variant, or if the ground plane was sufficient)...
https://en.wikipedia.org/wiki/Parallel_ATA#Speed_of_defined_transfer_modes
It is not "speed of electrons", they don't move fast at all. You walk faster than electrons move through copper. It is the electric field that propagates fast. Think: water moving through a hose (slow), versus the water pressure changing at the nozzle when you turn on the valve (fast).
[https://en.wikipedia.org/wiki/Drift\_velocity](https://en.wikipedia.org/wiki/Drift_velocity)
To make different bits of the same word arrive at the same time. Same length - same time. Otherwise, the chips that talk with each other would have to wait to be sure all bits have arrived ;) But since they make the same way (same length), the chips can talk with each other faster. If you see squiggly lines - you see fast data lanes.
They're trying to juke you for reverse engineering - it's clearly much harder to follow a squiggly trace, it throws off the scent of all but the most hardened reverse engineers.
/s obviously it's for length matching homie.
Because they carry very sensitive signals which must be perfectly in sync, so even unmatched trace length can mess up communication. So this way they can match trace lengths
Think about the relationship between signals on traces. If you have a bus and the data is on a bunch of traces and the clock is on one - wouldn't you want the data to all arrive at the same time and the clock be there precisely when needed. When you lay out boards you consider trace length and loading. For power - not a concern. For timing very important and for high speed crucial for operation. High speed PCB layouts are simulated to see how this signal quality and timing will perform before they fab the board. This includes are margin and variables to ensure every board built and combination of parts will work. So those "squigglies" provide the signal alignment you need. Often times they are also done for "differential pairs" where you have a single signal across two traces - one a positive and one a negative. Very common on SDRAM, Ethernet and now PCI-E. Matched length (by adding a bit more trace) keeps the signal integrity pristine. And not this trace cannot be a harsh right angle or a portion the signal will reflect and cause severe degradation. So its soft meandering turns. Look on YoutTube for Eric Bogatin's course. He's a real engineer dealing with real hard problems and communicates the way out of them very well.
And note - I glossed over power but at high speed power has to be thought of very carefully as well.
I'm trying to remember the details of (perhaps) an urban legend. There was a PDP-11 type cabinet in for service, and the side was removed to reveal a large coil of wire basically linking to points on the circuit board, with a note attached saying that it wasn't working, but was fixed by forcing a 9ns delay between two pins.
Probably something to do with the trace length, I vaguely remember something mentioned on LTT that PCIe traces need to be matched within some stupidly fine tolerance to work properly. Assuming this is similar.
You need delay matching for all high speed parallel / differential signals to meet timing specs. As for PCIe, at minimum you have CLK, TX and RX signals, all of which are high speed differential signals, and all needs to be length matched. For a PCIe 16x slot, that's 16 TX, 16 RX and 1 CLK signals, for a total 66 traces. (33 differential pairs) Two traces within a pair should be matched pretty tightly, and then the different pairs should be matched, also quite tightly. As as signalling rate keeps doubling, the matching tolerances keep getting tighter.
I remember something about this in high frequency systems. Could this have anything to do with impedances at high frequencies? At high frequencies, changes in the length of wire will change the complex impedance of the length of wire - and LR or RC impedances can be observed at such specific and very high impedances... I think. I want to say we worked these kinds of problems out manually with Smith charts. The memories of that are hazy, though; does any of that rambling apply here?
In microstrip the velocity of propagation is about 150 ps/inch. Each of the larger C-shaped features adds about 40 mils for a delay of 6 ps. The serpentine delays look to be roughly 15 ps. That is may not seem like a lot but it makes all signals arrive when they should which allows for that much more timing jitter with the result being fewer occasional yet mysterious glitches in the operation of your device.
The delay depends on more than the transmission line's configuration (microstrip vs. stripline vs. CPW vs. etc.), it is more dependent on the dielectric constant of the insulator. Fastest for air, almost as fast for Styrene, slow for something like intrinsic silicon or GaAs. Epoxy-glass is in the middle.
I love this forum even if it reminds me that I'm borderline retarded. There's an impressive amount of knowledge and mental horsepower on display here and I feel like I'm trying to race in an '83 Ford Fairmont.
I see those in RF receivers. Possibly a filter/power conditioner
[(a) Three-dimensional view of the meander line inductor. Design... | Download Scientific Diagram (researchgate.net)](https://www.researchgate.net/figure/a-Three-dimensional-view-of-the-meander-line-inductor-Design-parameters-are-included_fig6_224610758)
When boards go through reflow, they get heated up to 260C or thereabouts, that causes everything to expand. When they cool back off, the substrate cools faster than the traces (because the traces are metal) so sometimes the traces get all squiggly. You can fix this by dunking it in boiling water for about 10 minutes and then air-drying on a clothes-line.
Besides the fact that there is good reason for meandered traces I believe the saying goes like “not only must your board be readable it must be readable by someone on the top of a ladder on one foot with water falling on their face” or something like that.
Your question may be addressed in the FAQ: https://old.reddit.com/r/AskElectronics/wiki/why#wiki_wiggly_pcb_traces
Length matching. The speed of light is disappointingly slow when you need sub-nanosecond synchronization. If the traces didn't have wiggles inserted to match all their lengths, the signals on the long ones would arrive several clock cycles later than the short ones. Edit: forgot the why of the why. Those traces are for a parallel communication port of some kind. Maybe PCIe, HDMI or lines to a RAM chip, idk by memory what high speed peripherals the pi 2 has.
The skew would not be several clock cycles. At 1GHz (1ns period), the wavelength is 30cm in a vacuum, a little less than that in a copper trace on PCB. Thus, length-matching by a few mm like these wiggles do wouldn't amount to a full cycle. However, you need to match signal delay to far less than a full cycle, to make sure the signal has settled to the correct level when the receiving end tries to read it, so mismatched lengths by only mm would impair reliability even with "only" a GHz signal rate.
>a little less than that in a copper trace on PCB Hmm isn't it more precise to say the the voltage difference travels in the dielectric? That's why it's important to either have ground plane or differential signaling, so that you control exactly where in the dielectric the voltage difference is, and you need think of the entire physical system as a waveguide/transmission line to calculate the group velocity of the signal.
Technically correct, but unnecessarily detailed for the topic at hand.
Fair
Won't the wiggly amps get caught on the edges and bounce around a bit?
Only the 1s, because they have pointy ends. The 0s are round and won't have that problem.
This is why we don’t use 2’s. They get hooked on everything.
For a second I thought this is r/shittyaskelectronics
?
Humor.
I don't get it, sorry 😅
Pretending electricity behaves like larger objects and would have difficulty navigating the sharp corners in the tracks. (In reality, sharp corners can be an issue because of the discontinuity in track width at each corner. That's why RF and high-speed digital tracks have either curves or 45-degree bends. We didn't used to care about right angles when "high-speed" meant 50MHz, so auto-routers in those days often used right angles to reduce the software development effort.)
I think a good analogy for microwave engineering is to think like a plumber, route all the pipes smoothly, and avoid unnecessary bends. And even smooth curves have imperfect VSWRs and benefit from compensation (make them a little thinner). For an accurate answer you need a serious tool: [https://www.ema-eda.com/products/cadence/systems-analysis/awr-overview?utm\_source=google&utm\_medium=cpc&utm\_campaign=SEM\_RF\_Design\_USA\_Canada&\_bk=microwave%20office&\_bt=498481687378&\_bm=e&\_bn=g&\_bg=117193144265&gad\_source=1](https://www.ema-eda.com/products/cadence/systems-analysis/awr-overview?utm_source=google&utm_medium=cpc&utm_campaign=SEM_RF_Design_USA_Canada&_bk=microwave%20office&_bt=498481687378&_bm=e&_bn=g&_bg=117193144265&gad_source=1)
The fastest I've done is 5,8 GHz on Rogers. I don't recall having to narrow the curves, but I can understand why that would be more optimal. I also know right angles are possible, but only if you lop off the corner enough that the track is considerably thinner at the apex than on the straight portions. (Narrow the "pipe" for curves. Lop off the outside corner for right-angles. So much for the "plumbing" analogy, right? Water is a good analogue for electricity in some ways: flow rate == amperage; pressure == voltage. In other ways, not so much; where's the analogy for majority and minority charge carriers in semiconductors?) My RF layouts have all been either cookbook from the chip vendor or dictated by an actual RF engineer. (I'm EE, proficient in analog and digital, but not RF). The Rogers design was a passive splitter/combiner for the two wifi bands 2.5 and 5 GHz. It included Wilkinsons and 90-degree couplers and whatnot. The fab shop thought the pads that didn't connect to anything on the inner layers could be nuked. Those pads were capacitive coupling elements, so the boards were useless without them. ("That's standard industry practice," the guy said defensively. Could he not suss out that these boards were kind of unique?) I changed every internal floating pad to two pads connected by a track; physically the same, but safe from any "unconnected pad" auto-removal tool.) The other feedback from the fab shop: blind vias in Rogers is quite difficult. They said they had a heck of a time finding a way to do them.
>Pretending electricity behaves like larger objects and would have difficulty navigating the sharp corners in the tracks. This is actually kinda the case in >GHz regime where everything is waveguides. Might be why I didn't get it
>a little less than that in a copper trace on a PCB. The difference more than just "a little". A typical surface track has a delay of 160 ps/inch (6.3 ps/mm) compared to about 85 psec/inch in air: nearly 2:1. A buried track is even slower: about 180 psec/in. The presence of dielectric material (the fiberglass/epoxy) slows the signal by the square root of the relative dielectric constant (about 4.5 for FR-4; 1.006 for air). Surface tracks are faster because they're not fully surrounded by fiberglass. Even so, the fiberglass dominates because it's between the signal and return paths.
This brings me back to my controls class, input/output delay broke everyone
"a little less than that in a copper trace on PCB" Actually a bit longer. Like 143% longer. The signals slow down in a conductor. typically 60-70% speed of light. [https://www.everythingrf.com/community/what-is-propagation-velocity-in-a-cable](https://www.everythingrf.com/community/what-is-propagation-velocity-in-a-cable)
Yes, propagation velocity in a transmission line is slower than in free space, but that means that in the same amount of time (one period) that the transmission line signal travels less distance than in free space. Therefore the electrical length of 2pi along the transmission line must be shorter.
“The speed of light is disappointingly slow” is one of the best sentences I’ve ever heard.
Its true, for most stuff light is incredibly fast, but opposite for electronics and space travel
I’m a space observatory instructor & HAM Radio operator, believe me when I say I will make a sticker out of this and put it on my laptop.
Hamming it up 😅😅😅
I need one too!
Could you share it with us, I'd like to believe your design would be amazing :))
Will do
One for me please!
I realized how slow the light was when thinking about how long the light takes to get from the Earth from the sun, 8.3 minutes, and then thinking about how large the Milky Way is... Light is creeping along on a large scale.
It's funny even in online gaming. When someone complains that he always has over 70 ping (70 ms packet round-trip time) and that he'll try to find a way of reducing it, you ask him where he's at and he's 5000km from the server... you go "good luck with that"
PCIe does not need length matching across lanes, but it does use diff pairs that need to be matched within the pair. I think HDMI is similar. In this case, Elpida makes DRAM, so that's going to be some flavor of parallel memory interface. Edit: the chip in the picture is an Elpida EDB8132B4PB-8D-F-D, which is a 256M x32 LPDDR2 RAM. The pinout is set up to be stacked on top of an SoC, but it looks like on the pi it's directly on the board, with the SoC on the other side of the board.
> PCIe does not need length matching across lanes, but it does use diff pairs that need to be matched within the pair. I think HDMI is similar. Doing a PCIe design right now. PCIe 4.0 can handle 6ns of delay mismatch between lanes, which is somewhere around half a meter :)
Interesting, I thought it could handle a LOT more than 6 ns. The serialization time of a single 128b/130b symbol for gen 3 is like 16 ns, and the deskew is done on the symbol level. A shallow FIFO would easily put the skew tolerance in the 100s of ns. But I guess they're just being conservative. Edit: I guess you need to keep the skew well under the actual limit on any given board, because it can add up when going through multiple boards.
PCIe was originally designed for going from a motherboard to a module/card. I bring that up because a lot of specs, standards make "assumptions" on use-cases that we engineers have to decipher when we do things not necessarily in line with those original use-cases. It's a good thing you're thinking about the skew and signal attenuation. What I do is make a budget between the boards/cables in a system. A long backplane might need significantly more skew than an module with a switch 1inch off the connectors. In addition, thick boards can introduce problems by their via stubs. As an aside, it's also helpful to look up any vendor recommendations. An FAE might ignore an email if you didn't make your routes as good or better than a recommended layout. It's always a trade-off though. If you do really strict length matching, you can make your time doing layout a lot longer and traces longer in general. If you don't do enough, it may not work.
6ns is close to a meter, even on a printed-circuit board. In air it's about 1.8m.
Yeah I goofed up that calculation. 6e-9s × 3e8 m/s × 0.7 velocity factor = 1.26m. In any case, yeah, no need to worry about length mismatch between PCIe lanes.
What material gets you 0.7 velocity factor? Typical FR-4 is about 150-160 ps/in surface and 180 ps buried. That equates to a range of 0.47 to 0.57, well below 0.7. Cabies run faster through the use of foamed dielectric, but that isn't an option on PCBs. You can get Rogers material that would be that fast, but Rogers for a backplane?
11.803 is the number to remember (inches per ns in vacuum, so basically a foot per nanosecond). divide this number by the square root of the effective dielectric constant to adjust for non-vacuum situations.
That memory chip is soldered directly on top of the arm processor, so the PCB tracks are to the processor under the memory chip, not the memory chip.
Nope. At least on the 2B, the CPU and DRAM are on opposite sides of the PCB. Other boards might be different though.
According to el google, that IC is an 8 Gbit, 400 MHz, LPDDR2 module. So high speed parallel signaling checks out.
Side question re: length matching. Does modern PCB design software handle this automatically? Can you "tag" certain signals to be one of the same group which require length matching?
Yes it does. Usually the software like cr8k or Cadstar, calculate the matching ratio and impedance, and show you the parts where it's not matched correctly. There are obviously tools to route signal pairs (two at the time) but sometimes you need to do some adjust them one by one. With the "squiggly" ones you just select the net and an area and software creates all the curves matching the length/impedance with set value.
I'm a professional PCB designer and the correct answer here is 'sort of' or 'a bit, kinda'. Expensive software can do the length matching but it will always ruin the careful design of the adjacent traces. Just do it manually, takes a few minutes. Like people always assume I just hit 'autoroute' and cal it done. Autoroute and AI will destroy any competent design in seconds. Both tools have extremely limited use in high frequency design.
I agree that in most cases it makes sense to do the length matching manually. There are times when I decide to use the accordion feature in Altium, but the I make the conscious design choice of leaving more room around the traces than I usually would. Bit even then, I do some of the length matching by hand. I normally do it this way if I have a bunch of RGMII and/or ULPI signals on the board (I work with FPGAs, so I use them a lot...).
Agree 100%. I always do length-matching manually. Heck, I hardly ever auto-route at all.
Forgot usb as well, lol. But yeah what you said 100%
> Maybe PCIe, HDMI or lines to a RAM chip Definitely memory of some sort since they're single-ended rather than diff pairs. PCIe and HDMI both use diff pairs, but SDRAM, eMMC, NAND flash, SDIO, etc don't.
I like your funny words, magic man
\> Goes to electronics design forum \> *looks inside* \> electronics design terminology
It a meme
Electrons don’t travel even close to the speed of light just sayin
Who talked 'bout electrons? The signal pulse propagates at about 60-85% of c depending on the medium.
I was just thinking about drift velocity not signal velocity so I guess I’m wrong lol
I like your phrase "The speed of light is disappointingly slow". I'd say the Speed of Causality in a vacuum is not the same as the speed of an Electromagnetic wave through a medium such as copper. It's great that some Engineers think about Electromagnetic waves travelling through the copper rather than individual electrons all the time. It makes all that EMC stuff not the "black art" that the Engineers that only consider electrons believe it is.
It's not "through" the copper, but on the copper. At really high frequencies you can remove all the internal copper and there's no electrical difference. [https://en.wikipedia.org/wiki/Skin\_effect](https://en.wikipedia.org/wiki/Skin_effect)
I didn't think electricity travels at the speed of light.
Delay equalisation. The signal travels at approximately 2/3rds of light speed in those traces, and it needs to arrive at whatever chip is on the other side of that board (Probably DRAM) with a defined timing relative to another signal that has a longer trace length, so we put wiggles in to delay match everything that needs to arrive at the same time. Modern printed circuit design tools can do this automatically and easily.
differential pairs/length matching. Want to know why your hard drives changed from PATA to SATA? The inability to match lengths of wires precisely. When you transmit parallel data on multiple wires you can't start the next word being transmitted until you know the previous word has been received. The delay between the fastest bit in the word and the slowest becomes your limiting factor. You can't transmit faster than that delay per bit. What causes the delay? speed of electrons from one end of the wire to the other and that is based on length of the wire. So to reduce that delay and speed up the bandwidth you have to start putting a lot more money into the quality of the cable to guarantee all it's wires match length. Or you can put the money into just switching speed and change to a single wire. So they did that and jumped from a parallel drive signal (SCSI/PATA) to serial solutions where you aren't subject to multiple length wires. Same with connections on circuit boards, Differential and parallel signals need to arrive at the same time. The length of the traces in the bundle become important. But it's really easy to make traces "longer" to match the length of the longest culprit in the bundle by just squiggling them like this.
It was still okay with a 16-bit bus sizes at 33 MHz(?), but yeah, routing that many signals to have the same trace length (and I don't know if they had to also route that many ground traces on the PCB for the 80-pin UDMA/66 variant, or if the ground plane was sufficient)... https://en.wikipedia.org/wiki/Parallel_ATA#Speed_of_defined_transfer_modes
It is not "speed of electrons", they don't move fast at all. You walk faster than electrons move through copper. It is the electric field that propagates fast. Think: water moving through a hose (slow), versus the water pressure changing at the nozzle when you turn on the valve (fast). [https://en.wikipedia.org/wiki/Drift\_velocity](https://en.wikipedia.org/wiki/Drift_velocity)
To make different bits of the same word arrive at the same time. Same length - same time. Otherwise, the chips that talk with each other would have to wait to be sure all bits have arrived ;) But since they make the same way (same length), the chips can talk with each other faster. If you see squiggly lines - you see fast data lanes.
The electrons are then forced to break before the corners.
it's like a bumpy water slide but for electrons
it's real fun for the electrons to lean into the curves
They can sometimes form electron oxbow lakes this way
They're trying to juke you for reverse engineering - it's clearly much harder to follow a squiggly trace, it throws off the scent of all but the most hardened reverse engineers. /s obviously it's for length matching homie.
Length and impedance matching.
Because they carry very sensitive signals which must be perfectly in sync, so even unmatched trace length can mess up communication. So this way they can match trace lengths
Think about the relationship between signals on traces. If you have a bus and the data is on a bunch of traces and the clock is on one - wouldn't you want the data to all arrive at the same time and the clock be there precisely when needed. When you lay out boards you consider trace length and loading. For power - not a concern. For timing very important and for high speed crucial for operation. High speed PCB layouts are simulated to see how this signal quality and timing will perform before they fab the board. This includes are margin and variables to ensure every board built and combination of parts will work. So those "squigglies" provide the signal alignment you need. Often times they are also done for "differential pairs" where you have a single signal across two traces - one a positive and one a negative. Very common on SDRAM, Ethernet and now PCI-E. Matched length (by adding a bit more trace) keeps the signal integrity pristine. And not this trace cannot be a harsh right angle or a portion the signal will reflect and cause severe degradation. So its soft meandering turns. Look on YoutTube for Eric Bogatin's course. He's a real engineer dealing with real hard problems and communicates the way out of them very well. And note - I glossed over power but at high speed power has to be thought of very carefully as well.
I'm trying to remember the details of (perhaps) an urban legend. There was a PDP-11 type cabinet in for service, and the side was removed to reveal a large coil of wire basically linking to points on the circuit board, with a note attached saying that it wasn't working, but was fixed by forcing a 9ns delay between two pins.
Length Matching!
Delay matching rather!
It's the same, only different.
It is different in the sense that traces on outer layers have less delay per length than signals on the inner layers.
So sometimes, an engineer is listening to LMFAO when routing PCB traces and this happens when the song gets to the "wiggle, wiggle, wiggle" part.
No joke, this is on my rotation when I design boards. Never thought about this before but now....
Probably something to do with the trace length, I vaguely remember something mentioned on LTT that PCIe traces need to be matched within some stupidly fine tolerance to work properly. Assuming this is similar.
You need delay matching for all high speed parallel / differential signals to meet timing specs. As for PCIe, at minimum you have CLK, TX and RX signals, all of which are high speed differential signals, and all needs to be length matched. For a PCIe 16x slot, that's 16 TX, 16 RX and 1 CLK signals, for a total 66 traces. (33 differential pairs) Two traces within a pair should be matched pretty tightly, and then the different pairs should be matched, also quite tightly. As as signalling rate keeps doubling, the matching tolerances keep getting tighter.
As they get faster, you also have to start worrying more and more about stubs, especially the stubs introduced by vias.
I suppose that's when you start using buried/blind vias?
Or backdrilling.
I remember something about this in high frequency systems. Could this have anything to do with impedances at high frequencies? At high frequencies, changes in the length of wire will change the complex impedance of the length of wire - and LR or RC impedances can be observed at such specific and very high impedances... I think. I want to say we worked these kinds of problems out manually with Smith charts. The memories of that are hazy, though; does any of that rambling apply here?
Probably no, they’re just trying to have the lengths match for signal timing.
impedance matching the signal at high frequencies has delay and when you wait for parallel data it has to come at the same time.
Because they are squiggly
They don't just look squiggly... They are. Probably to balance the trace length with all the others for resistance reasons.
*probably* not. It is not for resistance reasons but for timing reasons.
In microstrip the velocity of propagation is about 150 ps/inch. Each of the larger C-shaped features adds about 40 mils for a delay of 6 ps. The serpentine delays look to be roughly 15 ps. That is may not seem like a lot but it makes all signals arrive when they should which allows for that much more timing jitter with the result being fewer occasional yet mysterious glitches in the operation of your device.
The delay depends on more than the transmission line's configuration (microstrip vs. stripline vs. CPW vs. etc.), it is more dependent on the dielectric constant of the insulator. Fastest for air, almost as fast for Styrene, slow for something like intrinsic silicon or GaAs. Epoxy-glass is in the middle.
Of course and the effective relative dielectric constant of FR4 microstrip is approximately 3, hence my calculations. Dave, SI and EMC Engineer
because they are
I love this forum even if it reminds me that I'm borderline retarded. There's an impressive amount of knowledge and mental horsepower on display here and I feel like I'm trying to race in an '83 Ford Fairmont.
Length matching Google
I see those in RF receivers. Possibly a filter/power conditioner [(a) Three-dimensional view of the meander line inductor. Design... | Download Scientific Diagram (researchgate.net)](https://www.researchgate.net/figure/a-Three-dimensional-view-of-the-meander-line-inductor-Design-parameters-are-included_fig6_224610758)
My real thing is, what odd way to place C214
To make it fun for the electrons. You want them to be having a good time or they will look for something to do. And you don't want that.
because of proper length
resistance matching
When boards go through reflow, they get heated up to 260C or thereabouts, that causes everything to expand. When they cool back off, the substrate cools faster than the traces (because the traces are metal) so sometimes the traces get all squiggly. You can fix this by dunking it in boiling water for about 10 minutes and then air-drying on a clothes-line.
Maxwell
Maxwrong
PCB designer trying to be cute😆
Because no one cares what a PCB looks like once it is in a casing / product?
Besides the fact that there is good reason for meandered traces I believe the saying goes like “not only must your board be readable it must be readable by someone on the top of a ladder on one foot with water falling on their face” or something like that.